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description the cxa1946aq/ar is a serial control electronic volume ic designed for use in audio systems. features loudness volume control (0db to ?7db in 1db step, db) balance tone control (15 steps, 2 bands, ?6db to +16db) fader (2db-step to ?0db, ?5db, ?5db, ?5db, ?0db, db) input selector (4 channels) gain can be set for each input channel (common for channels 3 and 4) serial data control (data, clk, ce) single 8v power supply zero-cross detection circuit (with timer) power-off mute volume control and tone control input/output pins are separate. absolute maximum ratings supply voltage v cc 13 v operating temperature topr ?0 to +85 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d qfp 350 mw (ta = 85?) lqfp 180 mw (ta = 85?) operating conditions supply voltage v cc 6 to 12 v ?1 cxa1946aq/ar e95602d7y electronic volume sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic) 48 pin lqfp (plastic)
?2 cxa1946aq/ar block diagram and pin configuration gain134 ldlc1 ldhc1 inao1 vrin1 vout1 tin1 tchc1 tclc11 tclc12 tco1 fdin1 gain234 ldlc2 ldhc2 inao2 vrin2 vout2 tin2 tchc2 tclc21 tclc22 tco2 fdin2 gain12 gain11 in14 in13 in12 in11 in21 in22 in23 in24 gain21 gain22 fnto1 reo1 ce clk dgnd gnd v cc vct data timer reo2 fnto2 loud vctbuff vctbuff vctbuff vctbuff vctbuff vctbuff shift register latch 100k 100k latch control 8db step volume 1db step volume tone fader volume 8db step volume 1db step tone fader loud input sw input sw zcdet 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1
?3 cxa1946aq/ar pin description pin no. symbol i/o resistance pin voltage equivalent circuit description 1 36 gain234 gain134 vct sets gain for in3 and in4. 36 1 gnd v cc 2 35 ldlc2 ldlc1 6.18k vct sets loudness low cut-off frequency. 35 2 v cc gnd 3 34 ldhc2 ldhc1 8.92k vct sets loudness high cut-off frequency. 34 3 gnd v cc 4 33 inao2 inao1 vct input selector output 4 33 gnd v cc ~
?4 cxa1946aq/ar 5 32 vrin2 vrin1 9.5k vct volume input 32 5 gnd v cc 6 31 vout2 vout1 vct volume output 31 6 v cc gnd 7 30 tin2 tin1 19k vct tone input 30 7 gnd v cc 8 29 tchc2 tchc1 5k vct sets tone high frequency. 29 8 gnd v cc pin no. symbol i/o resistance pin voltage equivalent circuit description
?5 cxa1946aq/ar 9 28 tclc21 tclc11 8k vct sets tone low frequency. 28 9 gnd v cc 10 27 tclc22 tclc12 8k vct sets tone low frequency. 27 10 v cc gnd 11 26 tco2 tco1 vct tone control output 26 11 gnd v cc 12 25 fdin2 fdin1 24k vct fader input 25 12 gnd v cc pin no. symbol i/o resistance pin voltage equivalent circuit description
?6 cxa1946aq/ar 13 24 fnto2 fnto1 vct front output 24 gnd 13 v cc 14 23 reo2 reo1 vct rear output 23 v cc gnd 14 15 timer sets timer. gnd 15 v cc 16 data serial data input gnd 16 v cc pin no. symbol i/o resistance pin voltage equivalent circuit description ~
?7 cxa1946aq/ar 21 clk serial clock input 17 vct vct center electric potential 18 v cc v cc + power supply 19 gnd gnd gnd 20 dgnd digital gnd gnd 21 v cc 22 ce latch enable input 22 gnd v cc 37 48 gain12 gain22 sets gain for in2. 48 37 v cc gnd pin no. symbol i/o resistance pin voltage equivalent circuit description vct ~ ~ ~
?8 cxa1946aq/ar 38 47 gain11 gain21 sets gain for in1. 47 38 gnd v cc 39 40 41 42 43 44 45 46 in14 in13 in12 in11 in21 in22 in23 in24 50k vct signal input 40 39 41 42 44 45 46 43 gnd v cc pin no. symbol i/o resistance pin voltage equivalent circuit description ~
?9 cxa1946aq/ar data format (a) data allocation fast bit last bit msb lsb d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 nop isw loud vrc1 vrf1 vrc2 vrf2 tone bass tone treble fader fader select
?10 cxa1946aq/ar (b) setting table nop setting value d1 d2 0 0 isw setting value d3 d4 in14/in24 in13/in23 in12/in22 in11/in21 1 1 0 0 1 0 1 0 vrc1/vrc2 setting value d6/d13 d7/d14 0 ? ?6 ?4 ?2 ?0 ?8 ?6 ?4 ?2 ?0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 d8/d15 1 1 0 0 1 1 0 0 1 1 0 0 0 d9/d16 1 0 1 0 1 0 1 0 1 0 1 0 0 vrf1/vrf2 setting value d10/d17 d11/d18 0 ? ? ? ? ? ? ? 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 d12/d19 1 0 1 0 1 0 1 0 loud setting value d5 on off 1 0
?11 cxa1946aq/ar tone bass/treble setting value d20/d24 d21/d25 14 12 10 8 6 4 2 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 d22/d26 1 0 1 0 1 0 1 0 fader setting value d28 d29 ?0 ?5 ?5 ?5 ?0 ?8 ?6 ?4 ?2 ?0 ? ? ? ? 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 d30 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 d31 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 boost/cut setting value d23/d27 boost cut 1 0 fader select reset reset is performed automatically when power is first supplied to the ic; there is no reset pin. the following table shows the respective statuses of various settings after a reset has been performed. however, from the time when power is first supplied until the first data transfer, keep ce high by pulling it up to vcc, etc. setting value d32 attenuation of front signal attenuation of rear signal 1 0 mode setting value input vrc1 vrf1 vrc2 vrf2 loud tone bass tone treble fader 1 ?db ?db off 0db 0db 0db, rear
?12 cxa1946aq/ar electrical characteristics (unless otherwise specified, vcc = 8v, ta = 25?) item symbol measurement conditions min. typ. max. unit current consumption total harmonic distortion output noise voltage maximum output voltage separation volume maximum attenuation low high bass max. boost gain bass max. cut gain treble max. boost gain treble max. cut gain low high input voltage range loudness input voltage i cc thd vn vom cs attm glb glh gbb gbc gtb gtc vsl vsh vin no signal 1khz, 5dbm output input shorted, a weight 1khz 1khz 1khz 100hz, vrc = ?6db 10khz, vrc = ?6db data, clk, ce in11 to 14, in21 to 24, vrin1, vrin2, tin1, tin2, fdin1, fdin2 8 72 85 7 5 14 14 14 14 0 3 1 20 0.005 7 90 90 8 6 16 16 16 16 25 0.01 10 9 7 18 18 18 18 1.5 6 v cc ? ma % vrms dbm db db db db db db db db v v v
?13 cxa1946aq/ar electrical characteristics measurement circuit fnto1 reo1 ce clk dgnd gnd v cc vct data timer reo2 fnto2 b 10k v24 ac fdin1 tco1 tclc12 tclc11 tchc1 tin1 vout1 vrin1 inao1 ldhc1 ldlc1 gain134 fdin2 tco2 tclc22 tclc21 tchc2 tin2 vout2 vrin2 inao2 ldhc2 ldlc2 gain234 gain12 gain11 in14 in13 in12 in11 in21 in22 in23 in24 gain21 gain22 0.0027 b a v6 ac b a 10 0.0022 0.047 10k 10k 10k 0.39 10 0.39 10 0.0027 10 10k 10k 0.0022 0.047 10k s6 of f on 10k 10k 1k 10k 0.01 v1 v ee 3 to 6v v cc 3 to 6v b a 1k v2 1k v3 10k 10k 1k v5 ac s1 on off 1k op amp 1k 220p vct-50mv s3 s2 b a v7 ac 10 s5-1 s4 b a v8 ac 10 s5-2 v23 ac v22 ac v21 ac v11 ac v12 ac v13 ac v14 ac b a b a b a b a b a b a b a s14 10k s13 10k s12 10k s11 10k s21 10k s22 10k s23 10k s24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 a
?14 cxa1946aq/ar application circuit 1 0.39 0.0027 10 10 0.39 10 0.0027 0.047 10 0.0022 33 0.01 10 0.047 10 0.0022 fnto1 reo1 ce clk dgnd gnd v cc vct data timer reo2 fnto2 fdin1 tco1 tclc12 tclc11 tchc1 tin1 vout1 vrin1 inao1 ldhc1 ldlc1 gain134 fdin2 tco2 tclc22 tclc21 tchc2 tin2 vout2 vrin2 inao2 ldhc2 ldlc2 gain234 gain12 gain11 in14 in13 in12 in11 in21 in22 in23 in24 gain21 gain22 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 10 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?15 cxa1946aq/ar application circuit 2 0.39 0.0027 10 10 0.39 0.0027 0.047 10 0.0022 33 0.01 0.047 10 0.0022 fnto1 reo1 ce clk dgnd gnd v cc vct data timer reo2 fnto2 fdin1 tco1 tclc12 tclc11 tchc1 tin1 vout1 vrin1 inao1 ldhc1 ldlc1 gain134 fdin2 tco2 tclc22 tclc21 tchc2 tin2 vout2 vrin2 inao2 ldhc2 ldlc2 gain234 gain12 gain11 in14 in13 in12 in11 in21 in22 in23 in24 gain21 gain22 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 10 10 10 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?16 cxa1946aq/ar 0 ?5 ?0 ?5 ?0 ? response [db] 10 100 1k 10k 100k frequency [hz] loudness characteristics vrc = 0db vrc = ?db vrc = ?6db vrc = ?4db 20 ?0 ?6 ?2 12 16 response [db] 10 100 1k 10k 100k frequency [hz] tone control characteristics 8 4 0 ? ? ?6db 0db +16db
?17 cxa1946aq/ar description of operation the cxa1946aq/ar is a serial control electronic volume ic designed for use in audio systems. the internal circuit of the ic consists of the following blocks: 1. input selector 2. volume 3. loudness 4. tone control 5. fader 6. vct buffer 7. serial data i/o 8. zero-cross detector (with timer) 9. power-off mute the operation of each block and notes on their use are described below. note that when the circuits for channels 1 and 2 are identical, the suffix ??is added to pin names and device names in order to distinguish between the two channels. 1. input selector there are two channels (stereo), each with four systems of input pins; the input selector selects one of those input systems. the gain between the input pins and the output pin of the input selector can be set independently for each input system, except the gain for inputs 3 and 4 is common. determine the gain for each system through the settings of the feedback circuit constants as shown in figs. 1 and 2. when each input gain is set to 1, short inaox and gain 1,gain 2,gain 34. the input impedance is 50k (typ.) for each input. the output impedance for inao1 and inao2 is low impedance (roughly 0 ). the gain is not affected by the load impedance. fig. 1. input selector (1) 50k inx4 50k inx3 50k inx2 50k inx1 vct gainx2 gainx1 gainx34 inaox
?18 cxa1946aq/ar fig. 2. input selector (2) 2. volume the volume circuit consists of two sections, an 8db/step section and a 1db/step section, as shown in fig. 3. this circuit also serves as a balance control because the volume for channel 1 and channel 2 can be set independently. to mute the output signal, send db data. the input impedance is 9.5k (typ.) for vrin1 and vrin2. the output impedance for vout1 and vout2 is low impedance (roughly 0 ). the volume step width and gain are not affected by the load impedance. 3. loudness the configuration of the loudness circuit is shown in fig. 3. c ldhcx and c ldlcx are connected externally, and the loudness frequency characteristics are determined by these constants. the relationships between c ldhcx /c ldlcx and the frequency characteristics are as follows: 1/f l = 2 c ldlcx r 1 1/f h = 2 c ldhcx r 2 the loudness characteristics are not affected by the load impedance of vout1 and vout2. loudness is turned on and off by serial data bit d5. fig. 3. volume and loudness 50k inx4 50k inx3 50k inx2 50k inx1 vct gainx2 gainx1 gainx34 inaox vrinx (input impedance 9.5k w ) 20k total 40k on loud r1 6.18k 25.7k r2 8.92k 4.98k 20k c ldhcx 0.0022 c ldlcx 0.047 ldhcx ldlcx voutx loudness volume off f h f l loudness frequency characteristics
?19 cxa1946aq/ar 4. tone control the configuration of the tone control circuit is shown in fig. 4. c tclcx2 and c tchcx are connected externally, and the tone control frequency characteristics can be changed by changing these constants. the relationships between c tclcx2 /c tchcx and the frequency characteristics are as follows: 1/f l = 2 c tclcx2 (r 3 //r 4 ) 1/f h = 2 c tchcx r 5 the maximum bass boost and cut can be made smaller than in the application circuit by connecting an external resistance to the tclcx1 pin in series, or else connecting an external resistance to c tclcx2 in parallel. (see fig. 5.) furthermore, the maximum treble boost and cut can be made smaller than in the application circuit by connecting an external resistance to c tchcx in series. (see fig. 6.) however, when these methods are used, variations in the absolute value of the cxa1946a internal resistance (20% max.) and in the external resistance will cause variations in the tone control characteristics. set these constants after studying all considerations carefully. note that when the method illustrated in the application circuit is used, variations in the internal resistance of the cxa1946a have no effect on the tone control characteristics. the input impedance is 19k (typ.) for tin1 and tin2. the output impedance for tco1 and tco2 is low impedance (roughly 0 ). the tone step width and gain are not affected by the load impedance. fig. 4. tone control tcox 14.1k 14.1k 12k tclcx1 tclcx2 c t clcx2 0.39 r4 8k bass cut on off on off boost 14.1k 14.1k 12k 10k 10k 10k 10k r5 5k cut on off on off boost treble tchcx c t chcx 0.0027 r3 8k f h f l tone control frequency characteristics input impedance 19k w tinx
?20 cxa1946aq/ar fig. 5. method for reducing bass boost/cut fig. 6. method for reducing treble boost/cut 5. fader the configuration of the fader circuit is shown in fig. 7. the fader operates by specifying the amount of attenuation for either the front or rear output signal and by specifying which output signal (front or rear) is to be attenuated. the input impedance is 24k (typ.) for fdin1 and fdin2. the output impedance for fnto1, fnto2, reo1, and reo2 is low impedance (roughly 0 ). the gain and fader step width are not affected by the load impedance. fig. 7. fader r4 8k tclcx1 tclcx2 c tclcx2 r3 8k (b) rexb r4 8k tclcx1 tclcx2 c tclcx2 r3 8k tinx (a) rexa r3 5k 10k 10k 10k 10k tchcx c tchcx rexc fdinx (input impedance 24k w ) fntox center att center att reox
?21 cxa1946aq/ar 6. vct buffer the internal circuit for the vct pin is shown in fig. 8. this circuit generates the electric potential for the center between vcc and gnd (vcc/2). the ic internal operation reference potential is equal to the output potential of vct buffer. the impedance for the vct pin (pin 17) is high since it is connected to a bypass capacitor. add an external buffer when using the electric potential of the vct pin as the external reference potential for the cxa1946. fig. 8. vct buffer 7. serial data i/o the serial data has a 32-bit structure as indicated in the specifications. data input is conducted using three inputs: data, clk, and ce. data is shifted in the cxa1946a internal shift register at the rising edge of clk. the data in the shift register is latched at the falling edge of ce. refer to this specification for details on the timing. the cxa1946a does not have a reset (initialize) pin. the internal shift register and latch are reset automatically when power is first supplied to the ic. to execute a reset at other times, send the data (statuses after reset ) shown in the item "reset" of this specification to the cxa1946a. 8. zero-cross detector (with timer) using the zero-cross detector, the internal latch data is overwritten the first time the input signal becomes roughly 0 after serial data is sent (after ce goes low). this operation reduces noise when overwriting data. although there are usually no problems when a normal audio signal is input, in rare cases there may be nothing except a large-amplitude input signal of the high band, causing the slew rate to become abnormally high; the zero-cross detection signal is not output in such a case because the zero-cross detector response speed is too slow. another rare situation would be that the zero-cross detection signal is output very infrequently because the input signal frequency is extremely low. in these types of instances, it is conceivable that the internal latch data will not be overwritten after data is sent, or that it will take much time until the data is overwritten. therefore, to an external observer it will appear that the data is not being overwritten regardless of the fact that data is being sent. as a countermeasure, the ic is designed to permit the internal latch data to be forcibly overwritten if the zero-cross detection signal is not output within a certain waiting period after the data is sent (after ce goes low). this function is called the ?imer.?if the zero-cross detection signal is output within a certain waiting period, the internal latch data is overwritten in synchronization with the zero-cross of the input signal. the waiting period mentioned above can be changed according to the value of the external capacitor connected to the timer pin. when the value of the capacitor is 0.01f, the waiting period is approximately 500s. 9. power-off mute when vcc goes below 5v, the output stage bias of the fader output pins fnto1, fnto2, reo1, and reo2 is turned off and the pins go to high impedance. this operation prevents popping noises caused by the output pin potential deviating from vcc/2 when the power is turned off. v cc 100k 100k vct 10
?22 cxa1946aq/ar connections and characteristics of each block in the application circuit, the signal path goes from the input selector to the volume (+loudness) to the tone control to the fader. the sequence of the blocks in the signal path can be changed because the i/o pins for each block are independent of each other. for example, it is possible to switch the sequence of the volume circuit and the tone control so that the signal path goes from the input selector to the tone control to the volume (+loudness) to the fader. when this connection method is used, the noise voltage in the fader output can be reduced in actual use because the noise and signal up to the tone control are attenuated by the volume. however, because the maximum output amplitude of the tone control circuit is limited by the supply voltage, care should be given to the setting of the input signal level. although blocks in the application circuit are linked either by coupling capacitors or by direct connection, it is also possible to insert external circuits between blocks. in this case, the gain will change according to the input impedance of the following block and the impedance of the external circuit. in addition, the input impedance of each block can vary by 20% due to the characteristics of the ic. consequently, the overall gain also varies. give careful consideration to the effects of this variation when setting the constants. the step widths (control characteristics) of the volume, tone control, and fader are not affected. timing chart t 1 t ck t su t h t 2 t l t ce ce clk data ce t 1 3 0.5 s t 2 3 0.5 s t ck 3 1.0 s t su 3 0.5 s t h 3 0.5 s t l 3 t t + 0.5 s (t t is the maximum value for the timer operation time) t ce 3 4.0 s d1 d2 d30 d31 d32 invalid timer waiting period setting chart (vcc = 6 to 12v, operating temperature = ?5? to 85?) timer pin capacitance c waiting peroid min. typ. max. c = 100pf c = 0.001f c = 0.01f c = 0.1f c = 1f c = 10f 3s 30s 300s 3ms 30ms 300ms 5s 50s 500s 5ms 50ms 500ms 9s 90s 900s 9ms 90ms 900ms thi dt h th b d f ld t hl t tth
?23 cxa1946aq/ar package outline unit: mm cxa1946aq sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g t note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).
?24 cxa1946aq/ar cxa1946ar sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 48pin lqfp (plastic) 9.0 0.2 * 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.5 0.08 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 0.1 0.1 0.5 0.2 a 1.5 ?0.1 + 0.2 0?to 10 detail a 0.2g lqfp-48p-l01 * qfp048-p-0707-a 0.1 note: dimension * ?does not include mold protrusion.

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